`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    02:54:02 02/28/2014 
// Design Name: 
// Module Name:    clock_div_25MHz 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clock_div(pixel_clk, clk_1KHz, clk_5Hz, clk_800Hz, clk_700Hz, clk);
	input clk;
	output reg pixel_clk, clk_1KHz, clk_800Hz, clk_700Hz, clk_5Hz;
	reg [1:0] div = 0;
	
	integer i,j,k,o;
	always @ (posedge clk) begin
		div <= div + 1'b1;
		pixel_clk <= div[1];
	end
	
	always @ (posedge pixel_clk) 
		begin
			if (i<125000)
				i<=i+1;
			else
				begin
					i<=0;
					clk_1KHz<=~clk_1KHz;
				end
			end
			
	always @ (posedge pixel_clk) 
		begin
			if (k<156250)
				k<=k+1;
			else
				begin
					k<=0;
					clk_800Hz<=~clk_800Hz;
				end
			end	

   always @ (posedge pixel_clk) 
		begin
			if (o<178571)
				o<=o+1;
			else
				begin
					o<=0;
					clk_700Hz<=~clk_700Hz;
				end
			end				
			
			
	always @ (posedge clk_1KHz) 
		begin
			if (j<8)
				j<=j+1;
			else
				begin
					j<=0;
					clk_5Hz<=~clk_5Hz;
				end
			end
		

endmodule
